1. Field of the Invention
This invention relates to computer systems and more particularly to buffer transfer apparatus for transferring data between a peripheral device and a host computer. The invention further relates to high performance adapter cards and disk controllers.
2. Description of the Relevant Art
High performance adapter cards such as disk controllers coordinate the transfer of data between a peripheral device and a host computer. A typical adapter card includes a RAM buffer, often in the form of a cache memory, which temporarily holds selected data prior to sending it to the host computer. For example, within a typical caching disk controller, when the host computer requests a sector which is not contained by the cache, the disk controller causes the sector to be read from the disk and to be transferred into the cache. When the transfer into the cache is complete, the disk controller initiates a transfer of the sector from the cache to the host computer. The sector of data is transferred into the cache to achieve high cache-hit rates during subsequent disk operations. However, the step of storing the data in the cache adds considerable latency to cache misses since the miss penalty is the sum of the disk latency, the disk transfer time, and the host transfer time. This latency is particularly noticeable within caching disk controllers since a disk cache is typically associated with a line size that is greater than the average request length (i.e., a typical cache line consists of several sectors). Thus the host must wait for both the requested data as well as unrequested data (that forms a complete cache line) to be stored in the cache before the requested data can actually be transferred to the host.
The problems described,above may be better understood with reference to FIGS. 1 and 2. FIG. 1 is a block diagram of a computer system 100 including a host processor 102 and a system memory 103 coupled to a caching disk controller 104 via a host bus 106. The caching disk controller 104 is coupled to a plurality of SCSI devices 06A-106D via SCSI buses 108 and 110. The caching disk controller 104 includes a bus bridge 120 coupled to a local processor 122 and a cache memory 124 via a local bus 126. A pair of SCSI processors 128 and 130 are further coupled to local bus 126.
FIG. 2 is a block diagram of the bus bridge 120 incorporated within the caching disk controller 104 of FIG. 1. The bus bridge 120 includes a host interface 202 coupled to host bus 106, and a local interface coupled to local bus 126. A host interface register file 206 and a DMA controller 208 are coupled between local interface 204 and host interface 202.
Referring collectively to FIGS. 1 and 2, the operation of caching disk controller 104 during a read request by host processor 102 is next considered. If host processor 102 desires to read a sector of data from one of the SCSI devices 106A-106D, a sector read request is transmitted by the host processor 102 and is written into the host interface register file 206 of bus bridge 120. Bus bridge 120 responsively asserts an interrupt to alert local processor 122 of the pending request. Local processor 122 subsequently reads the pending request within the host register file 206 and, upon determining that the current request is a read request, determines whether the requested sector is contained by cache memory 124. If the sector is contained by cache memory 124, a so-called cache "hit" has occurred, and the local processor 122 causes the DMA controller 208 of bus bridge 120 to initiate a direct memory access (DMA) operation to read the requested sector directly from cache memory 124. It is noted that the latency associated with such a read request when a cache hit occurs is extremely small since the cache memory 124 is implemented using memory devices having speeds that are comparable to the speed of host processor 102. As a result, if high cache-hit rates are maintained, excellent overall read performance may be achieved.
On the other hand, if the requested sector is not contained within cache memory 124, a so-called cache "miss" has occurred and the sector must be read from the appropriate SCSI device 106A-106D. It is noted that the latency associated with a read operation from a designated SCSI device 106A-106D is much greater than the latency associated with cache memory 124, particularly for situations in which SCSI devices 106A-106D are disk drives. After local processor 122 determines that a cache-miss has occurred, it determines which of the SCSI devices 106A-106D contains the requested sector. Local processor 122 then posts a read request to the appropriate SCSI processor 128 or 130. For example, if the requested sector is contained by SCSI device 106A, local processor 122 issues a read request directed to SCSI processor 128. SCSI processor 128 responsively obtains mastership of local bus 126 and initiates a cycle to transfer the line comprising the sector of data from SCSI device 106A to cache memory 124. When the transfer of the line of data into cache memory 124 is complete, the SCSI processor 128 asserts an interrupt to local processor 122. Local processor 122 responsively causes the DMA controller 208 of bus bridge 120 to initiate a direct memory access operation to thereby transfer the sector of requested data from cache memory 124 to system memory 103. This completes the transfer as originally requested by host processor 102.
It is noted that since the requested sector is stored in the cache memory 124, subsequent read and write operations to the line that includes that sector may be serviced directly by the cache. Significant improvements in read and write performance may thereby be attained. However, as mentioned previously, a drawback to the above-described caching technique is that when a cache-miss occurs, the requested sector of data is not transferred to system memory 103 until after the entire line of data has first been transferred from the SCSI device 106A-106D into the cache memory 124. Accordingly, the host processor 102 must wait not only for the line of data to be read from the SCSI device 106A-106D but also for the requested sector of data to be read from the cache memory 124. Accordingly, overall performance of the computer system may be degraded.